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August 2000 PRELIMINARY
ML6516244* 16-Bit Buffer/Line Driver with 3-State Outputs
GENERAL DESCRIPTION
The ML6516244 is a BiCMOS, 16-bit buffer/line driver with 3-state outputs. This device was specifically designed for high speed bus applications. Its 16 channels support propagation delay of 2.5ns maximum, and fast output enable and disable times of 7.0ns or less to minimize datapath delay. This device is designed to minimize undershoot, overshoot, and ground bounce to decrease noise delays. These transceivers implement a unique digital and analog implementation to eliminate the delays and noise inherent in traditional digital designs. The device offers a new method for quickly charging up a bus load capacitor to minimize bus settling times, or FastBusTM Charge. FastBus Charge is a transition current, (specified as IDYNAMIC) that injects between 60 to 200mA (depending on output load) of current during the rise time and fall time. This current is used to reduce the amount of time it takes to charge up a heavily-capacitive loaded bus, effectively reducing the bus settling times, and improving data/clock margins in tight timing budgets. Micro Linear's solution is intended for applications for critical bus timing designs that include minimizing device propagation delay, bus settling time, and time delays due to noise. Applications include; high speed memory arrays, bus or backplane isolation, bus to bus bridging, and sub2.5ns propagation delay schemes. The ML6516244 follows the pinout and functionality of the industry standard 3.3V-logic families.
FEATURES
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Low propagation delays -- 2.5ns maximum for 3.3V 2.25ns maximum for 5.0V Fast output enable/disable times of 5.0ns maximum FastBus Charge current to minimize the bus settling time during active capacitive loading 3.0 to 3.6V and 4.5 to 5.5V VCC supply operation; LV-TTL compatible input and output levels with 3-state capability Industry standard pinout compatible to FCT, ALV, LCX, LVT, and other low voltage logic families ESD protection exceeds 2000V Full output swing for increased noise margin Undershoot and overshoot protection to 400mV typically Low ground bounce design
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* This part is End of Life as of August 1, 2000.
BLOCK DIAGRAM
VCC OE A0 B0 B1 B2 B3
A1 A2 A3
GND 1 of 4
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ML6516244
PIN CONFIGURATION
ML6516244 48-Pin SSOP (R48) 48-Pin TSSOP (T48)
1OE 1B0 1B1 GND 1B2 1B3 VCC 2B0 2B1 GND 2B2 2B3 3B0 3B1 GND 3B2 3B3 VCC 4B0 4B1 GND 4B2 4B3 4OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 15 2 16 3 17 4 18 5 19 6 20 7 21 8 22 9 23 10 24 TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 20 34 19 33 18 32 17 31 16 30 15 29 14 28 13 27 12 26 11 25 2OE 1A0 1A1 GND 1A2 1A3 VCC 2A0 2A1 GND 2A2 2A3 3A0 3A1 GND 3A2 3A3 VCC 4A0 4A1 GND 4A2 4A3 3OE
FUNCTION TABLE
(Each 4-bit section)
INPUTS OE L L H 1Ai, 2Ai, 3Ai, 4Ai H L X OUTPUTS 1Bi, 2Bi, 3Bi, 4Bi H L Z
L = Logic Low, H = Logic High, X = Don't Care, Z = High Impedance
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ML6516244
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1OE 1B0 1B1 GND 1B2 1B3 VCC 2B0 2B1 GND 2B2 2B3 3B0 3B1 GND 3B2 3B3 VCC 4B0 4B1 GND 4B2 4B3 4OE
Output Enable Data Output Data Output Signal Ground Data Output Data Output 3.3V or 5.0V Supply Data Output Data Output Signal Ground Data Output Data Output Data Output Data Output Signal Ground Data Output Data Output 3.3V or 5.0V Supply Data Output Data Output Signal Ground Data Output Data Output Output Enable
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
3OE 4A3 4A2 GND 4A1 4A0 VCC 3A3 3A2 GND 3A1 3A0 2A3 2A2 GND 2A1 2A0 VCC 1A3 1A2 GND 1A1 1A0 2OE
Output Enable Data Input Data Input Signal Ground Data Input Data Input 3.3V or 5.0V Supply Data Input Data Input Signal Ground Data Input Data Input Data Input Data Input Signal Ground Data Input Data Input 3.3V or 5.0V Supply Data Input Data Input Signal Ground Data Input Data Input Output Enable
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ML6516244
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC ............................................................................. 7V DC Input Voltage .............................. -0.3V to VCC + 0.3V AC Input Voltage (PW < 20ns) ................................. -3.0V DC Output Voltage ................................... -0.3V to 7VDC Output Current, Source or Sink ............................. 180mA Storage Temperature Range...................... -65C to 150C Junction Temperature ............................................. 150C Lead Temperature (Soldering, 10sec) ...................... 150C Thermal Impedance (qJA) ..................................... 76C/W
OPERATING CONDITIONS
Temperature Range ........................................ 0C to 70C VIN Operating Range ................................... 3.0V to 5.5V
ELECTRICAL CHARACTERISTICS - 3.3V OPERATION
Unless otherwise specified, VIN = 3.3V, TA = Operating Temperature Range (Note 1).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF) tPHL, tPLH tOE tOD TOS CIN Propagation Delay Output Enable Time Output Disable Time Output-to-Output Skew Input Capacitance Ai to Bi OE to Ai OE to Ai 1.8 2.1 2.5 7.0 7.0 500 5 ns ns ns ps pF
DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = Open) VIH VIL IIH IIL IHI-Z VIC Input High Voltage Input Low Voltage Input High Current Input Low Current Three-State Output Current Input Clamp Voltage Logic high Logic low Per pin, VIN = 3V Per pin, VIN = 0V VCC = 3.6V, 0 < VIN < VCC VCC = 3.6V, IIN = 18mA Low to high transitions High to low transitions VCC = 3.6V, IOH = -2mA VCC = 3.6V, IOL = 2mA VCC = 3.6V, f = 0Hz, inputs = VCC or 0V 2.4 0.6 3 -0.7 80 80 2.0 0.8 300 300 5 -0.2 V V mA mA mA V mA mA V V mA
IDYNAMIC Dynamic Transition Current (FastBus Charge) VOH VOL ICC Output High Voltage Output LowVoltage Quiescent Power Supply Current
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
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ML6516244
ELECTRICAL CHARACTERISTICS - 5V OPERATION
Unless otherwise specified, VIN = 5V, TA = Operating Temperature Range (Note 1).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF) tPHL, tPLH tOE tOD TOS CIN Propagation Delay Output Enable Time Output Disable Time Output-to-Output Skew Input Capacitance Ai to Bi OE to Ai OE to Ai/Bi 1.6 1.9 2.25 7.0 7.0 500 5 ns ns ns ps pF
DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = Open) VIH VIL IIH IIL IHI-Z VIC Input High Voltage Input Low Voltage Input High Current Input Low Current Three-State Output Current Input Clamp Voltage Logic high Logic low Per pin, VIN = 4.5V Per pin, VIN = 0V VCC = 5.5V, 0 < VIN < VCC VCC = 5.5V, IIN = 18mA Low to high transitions High to low transitions VCC = 5.5V, IOH = -2mA VCC = 5.5V, IOL = 2mA VCC = 5.5V, f = 0Hz, inputs = VCC or 0V 4.5 1.2 3 -0.7 120 120 3.6 0.8 300 300 5 -0.2 V V mA mA mA V mA mA V V mA
IDYNAMIC Dynamic Transition Current (FastBus Charge) VOH VOL ICC Output High Voltage Output Low Voltage Quiescent Power Supply Current
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
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ML6516244
PERFORMANCE DATA 3.3V OPERATION
3.50 3.00 2.50 2.00 tPLH 1.50 1.00 0.50 0.00 tPHL 60 75pF 90 150pF 80 100pF 70
Tpd (ns)
ICC (mA)
50 40 30 20 10
50pF 30pF
30
50
75 LOAD (pF)
100
150
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
Figure 1. Propagation Delay over Load Capacitance: 30 to 150pF, VCC = VIN = 3.3V, 20MHz
Figure 2. ICC vs. Frequency (10 to 100 MHz) over Load, VCC = VIN = 3.3V
Figure 3. Ground Bounce: ML6516244, VCC = VIN = 3.0V VIN: tRISE = tFALL = 2ns
250
Figure 4. IDYNAMIC Current (FastBus Charge): ML6516244, VCC = VIN = 3.3V, 50pF load, 40mA/DIV, VIN: tRISE = tFALL = 2ns
0
200
-30
100
IOH (mA)
0 0.4 0.8 1.2 1.6 2.0
IOL (mA)
150
-60
-90
50
-130
0
-160 1.5
2.0
2.5 VOH (V)
3.0
3.5
VOL (V)
Figure 5a. Typical VOL vs. IOL for One Buffer Output
Figure 5b. Typical VOH vs. IOH for One Buffer Output
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ML6516244
PERFORMANCE DATA 5.0V OPERATION
3.00 100 100pF 2.50 150pF 80 75pF ICC (mA) 60 50pF 40 30pF 0.50 20
2.00 Tpd (ns) tPHL 1.50 tPLH 1.00
0.00
30
50
75 LOAD (pF)
100
150
0
0
20
40
60
80
100
FREQUENCY (MHz)
Figure 6. Propagation Delay over Load Capacitance: 30 to 150pF, VCC = VIN = 5.0V, 20MHz
Figure 7. ICC vs. Frequency (10 to 100 MHz) over Load, VCC = VIN = 5.0V
Figure 8. IDYNAMIC Current (FastBus Charge): ML6516244, VCC = VIN = 5.0V, 50pF load, 100mA/DIV, VIN: tRISE = tFALL = 2ns
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ML6516244
FUNCTIONAL DESCRIPTION
1OE 1A0 1B0 1B1 1B2 1B3
1A1 1A2 1A3
2OE 2A0 2B0 2B1 2B2 2B3
2A1 2A2 2A3
3OE 3A0 3B0 3B1 3B2 3B3
3A1 3A2 3A3
4OE 4A0 4B0 4B1 4B2 4B3
4A1 4A2 4A3
Figure 9. Logic Diagram
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
3A0
3A1
3A2
3A3
4A0
4A1
4A2
4A3
2OE
3OE
1OE
4OE
1B0
1B1
1B2
1B3
2B0
2B1
2B2
2B3
3B0
3B1
3B2
3B3
4B0
4B1
4B2
4B3
Figure 10. Logic Symbol
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ML6516244
ARCHITECTURAL DESCRIPTION
The ML6516244 is a 16-bit buffer/line driver with 3-state outputs designed for 3.0V to 3.6V and 4.5V to 5.5V VCC operation. This device is designed for Quad-Nibble, Dual-Byte or single 16-bit word memory interleaving operations. Each bank has an independently controlled 3state output enable pin with output enable/disable access times of less than 7.0ns. Each bank is configured to have four independent buffer/line drivers. Until now, these buffer/line drivers were typically implemented in CMOS logic and made to be TTL compatible by sizing the input devices appropriately. In order to buffer large capacitances with CMOS logic, it is necessary to cascade an even number of inverters, each successive inverter larger than the preceding, eventually leading to an inverter that will drive the required load capacitance at the required frequency. Each inverter stage represents an additional delay in the gating process because in order for a single gate to switch, the input must slew more than half of the supply voltage. The best of these 16-bit CMOS buffers has managed to drive 50pF load capacitance with a delay of 3.6ns. Micro Linear has produced a 16-bit buffer/line driver with a delay less than 2.5ns by using a unique circuit architecture that does not require cascade logic gates. The basic architecture of the ML6516244 is shown in Figure 11. In this circuit, there are two paths to the output. One path sources current to the load capacitance where the signal is asserted, and the other path sinks current from the output when the signal is negated. The assertion path is the Darlington pair consisting of transistors Q1 and Q2. The effect of transistor Q1 is to increase the current gain through the stage from input to output, to increase the input resistance and to reduce input capacitance. During an input low-to-high transition, the output transistor Q2 sources large amount of current to quickly charge up a highly capacitive load which in effect reduces the bus settling time. This current is specified as IDYNAMIC. The negation path is also the Darlington pair consisting of transistor Q3 and transistor Q4. With M1 connecting to the input of the Darlington pair, Transistor Q4 then sinks a large amount of current during the input transition from high-to-low. Inverter X2 is a helpful buffer that not only drives the output toward the upper rail but also pulls the output to the lower rail. There are a number of MOSFETs not shown in Figure 11. These MOSFETs are used to 3-state the buffers. For instance, R1 and R2 were implemented as resistive transmission gates to ensure that disabled buffers do not load the lines of which they are connected.
VCC R1 Q1 Q2 X1 IN X2 OUT
R2
M1 Q3 Q4
Figure 11. One Buffer Cell of the ML6516244
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ML6516244
CIRCUITS AND WAVE FORMS
VCC = 3V
ML6516244 DUT VIN 50pF IOUT VOUT
1.5V INPUT tPLH 1.5V OUTPUT tPHL 0V 0V 3V
tRISE AND tFALL INPUT = 2ns
Figure 12. Test Circuits for All Outputs
Figure 13. Propagation Delay
ENABLE CONTROL INPUT tOE OUTPUT LOW tOE OUTPUT HIGH
DISABLE VCC = 3V 1.5V tOD 3V
OUTPUT1 1.5V INPUT 1.5V
VOL + 0.3V VOL VOH VOH - 0.3V 0V tOD
tOS OUTPUTi i = 1 to 16 1.5V
Figure 14. Enable and Disable Times
Figure 15. Output Skew
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ML6516244
PHYSICAL DIMENSIONS
inches (millimeters)
Package: R48 48-Pin SSOP
0.620 - 0.630 (15.75 - 16.00) 48
PIN 1 ID
0.291 - 0.301 0.402 - 0.410 (7.39 - 7.65) (10.21 - 10.41)
1 0.015 - 0.025 (0.38 - 0.64) (4 PLACES) 0.025 BSC (0.63 BSC) 0.094 - 0.110 (2.39 - 2.79) 0 - 8
0.088 - 0.092 (2.24 - 2.34)
0.006 - 0.014 (0.15 - 0.36)
SEATING PLANE
0.008 - 0.016 (0.20 - 0.41)
0.024 - 0.040 (0.61 - 1.02)
0.005 - 0.010 (0.13 - 0.26)
Package: T48 48-Pin TSSOP
0.487 - 0.497 (12.37 - 12.63)
0.236 - 0.244 (6.00 - 6.20)
0.319 BSC (8.1 BSC)
PIN 1 ID
0.020 BSC (0.50 BSC)
0.047 MAX (1.20 MAX) 0 - 8
0.031 - 0.039 (0.80 - 1.00)
0.007 - 0.011 (0.17 - 0.27)
SEATING PLANE
0.002 - 0.006 (0.05 - 0.15)
0.020 - 0.028 (0.50 - 0.70)
0.004 - 0.008 (0.10 - 0.20)
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ML6516244
ORDERING INFORMATION
PART NUMBER ML6516244CR (OBS) ML6516244CT (EOL) TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE 48-Pin SSOP (R48) 48-Pin TSSOP (T48)
Micro Linear Corporation 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com
(c) Micro Linear 2000. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
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DS6516244-01

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